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[Other] jtag_verilog

Description: verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
Platform: | Size: 6047 | Author: 陈俊 | Hits:

[Other resource] verilog_usbblaster

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机
Platform: | Size: 1571611 | Author: 一王 | Hits:

[Other resource] rtl

Description: JTAG design verilog code.
Platform: | Size: 4124 | Author: assa | Hits:

[Other resource] BiDirectionalCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1027 | Author: hegs | Hits:

[Other resource] ControlCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1338 | Author: hegs | Hits:

[Other resource] InputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1192 | Author: hegs | Hits:

[Other resource] OutputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1416 | Author: hegs | Hits:

[Other resource] USB_jtag

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。
Platform: | Size: 1571611 | Author: 霍飘摇 | Hits:

[SourceCode] JTAG控制体verilog源码

Description:
Platform: | Size: 5010 | Author: changzhiheng | Hits:

[Other resource] JTAG控制体verilog源码

Description:
Platform: | Size: 5010 | Author: changzhiheng | Hits:

[VHDL-FPGA-Verilog] ControlCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] InputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] TAP3

Description: JTAG TAP Statemachine verilog code
Platform: | Size: 1024 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] TAP4

Description: JTAG TAP Statemachine verilog code
Platform: | Size: 1024 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] JTAGsoftcoredesignandsimulation

Description: 关于jtag软核设计与仿真的资料 利用verilog实现，并对仿真进行了说明-Jtag soft on information design and simulation using verilog implementation, and simulation are described
Platform: | Size: 391168 | Author: 思根 | Hits:

[VHDL-FPGA-Verilog] jtag-Verilog

Description: JTAG verilog code for xilinx fpga
Platform: | Size: 2048 | Author: headayt | Hits:

[VHDL-FPGA-Verilog] Using-JTAG-PROMs-for-data-storage

Description: Xilinx FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code
Platform: | Size: 158720 | Author: 赵齐 | Hits:

[VHDL-FPGA-Verilog] jtag

Description: verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
Platform: | Size: 435200 | Author: 张一凡 | Hits:

[VHDL-FPGA-Verilog] JTAG_Example0_Verilog

Description: 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
Platform: | Size: 386048 | Author: ZhouGuofei | Hits:

[VHDL-FPGA-Verilog] ARM_SOC

Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
Platform: | Size: 688128 | Author: ldz13180882132 | Hits:
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